library ieee;
use ieee.std_logic_1164.all;

entity mplex4x1 is
port(a,b,c,d:in std_logic;
	s:in std_logic_vector(1 downto 0);
	f:out std_logic);
	
end mplex4x1;


architecture bhv of mplex4x1 is
begin

f<= a when s="00" else
	b when s="01" else
	c when s="10" else
	d when s="11" else
	'-';

end bhv;